1. Field of the Invention
This invention relates to a burn-in test for a semiconductor memory device, and in particular, to a semiconductor memory device to be applied to defect screening of a transfer transistor constituting a memory cell.
2. Description of the Related Art
In a process of manufacturing semiconductor devices, in order to secure the reliability of them, screening is performed to detect and remove a device latently having a defect. Such screening chiefly employs "electric field acceleration" in which a voltage higher than in an usual case is applied, and "temperature acceleration" in which heat of a temperature higher than in an usual case is applied. Further, a burn-in test in which the electric field acceleration and temperature acceleration are carried out simultaneously is employed in many screening cases.
The burn-in test is effective to a device which may erroneously operate in an initial stage. When a semiconductor memory device is screened out by a burn-in test, many of the word lines of the device contained in a package are simultaneously accessed in the order of address at high temperature and voltage. In general, about 10000 memory cells are simultaneously tested at high temperature and voltage. Thus, the operation cycle of a burn-in test mode is extremely longer than the minimum operation cycle of the semiconductor memory device. Specifically, the minimum operation cycle of the memory device is about 150 nsec, while the operation cycle of the burn-in test mode is about 1.5 .mu.sec.
In a semiconductor memory device, in particular in a DRAM, the overall memory cell array is divided into a plurality of memory cell arrays which operate individually, so as to reduce the charge/discharge amount of a maximum bit line. In this structure, only some of the memory cell arrays are operated in response to an address signal input from an external device.
Further, in the DRAM, the number of cycles during which its particular refresh operation is performed is set. Accordingly, the number of word lines to be able to be accessed in one cycle is necessarily determined by the refresh cycles. In the case of a 4M-bit DRAM, for example, the refresh cycle number is set to 1024/16 ms. If the number of word lines is 4096, it is necessary to select four word lines in each cycle irrespective of how the whole memory cell array is divided. Thus, the larger the number of divided memory cell arrays, the less the charge/discharge amount of each bit line.
FIG. 11 shows a semiconductor memory device. This memory device is divided into e.g. four memory cell arrays CA1-CA4, and only two of the memory cell arrays are operated when the device is turned on. Address signals Ai and /Ai (hereinafter "/" indicates an inverse signal) are used to select only two of the memory cell arrays. If the address signal Ai is of high level, left two memory cell arrays CA1 and CA2 are selected, while if it is of low level, right two memory cell arrays CA3 and CA4 are selected.
FIG. 12 shows in detail one of the memory cell arrays shown in FIG. 11. A memory cell array 10 has a plurality of transfer transistors Tr and capacitors C. The address signal Ai and a word-line driving voltage WDRV are supplied to an AND circuit 11. The output signal of the AND circuit 11 is supplied to a row decoder 12, which in turn controls the word line WL of the memory cell array 10. The address signal Ai is also supplied to a sense amplifier 13, a column decoder 14, and an inputs/output buffer 15. The amplifier 13 is connected to the decoder 14 and buffer 15. Thus, the address signal Ai selects word lines at the time of refresh operation or other operations, restores cell data, reads data from a bit line corresponding to a column address signal, and controls to write data into a bit line. It is possible to commonly use the column decoder 14 for the overall memory cell arrays or some of them. In this case, it is not necessary to control the decoder 14 by the address signal Ai.
FIG. 13 shows the conventional word-line booster circuit. This booster circuit controls one of the word lines included in the memory cell arrays selected by the address signal Ai. In FIG. 13, an element corresponding to that shown in FIG. 12 is denoted by a corresponding reference numeral. Address signals An and /An are supplied to the input terminal of an OR circuit OR. The output terminal of the OR circuit is connected to an end of a boosting capacitor C1, which outputs the word-line driving voltage WDRV from the other end thereof. The driving voltage WDRV is supplied to an end of the current path of the transistor constituting the AND circuit 11.
In the above structure, the row decoder 12 supplied with each of the address signals Ai-An selects a corresponding word line. It is necessary in the DRAM to increase the potential of the word line to a value higher than V.sub.CC +V.sub.TH (V.sub.TH is the threshold voltage of the memory cell transistor; V.sub.CC is a power source potential) so as to resupply the power source potential V.sub.CC to each memory cell. To this end, after detecting that the address to be input to the row decoder 12 is determined, the potential of a corresponding word line is increased to a predetermined value by the boosting capacitor C1. The capacity of the capacitor C1 is calculated on the basis of the capacities of word lines selected during operation of the device, and a predetermined potential to which the word lines should be increased.
As is aforementioned, screening of a semiconductor memory device by a burn-in test is performed by successively accessing word lines in the order of address. In the burn-in test mode, however, successive accessing of word lines is disadvantageous in that the transfer transistor of a memory cell connected to each word line is supplied with a voltage stress at very lower frequency than a transistor in the peripheral circuit.
Specifically, in the case of 4M-bit DRAM, the number of the overall word lines is 4096, and the number of word lines selected in one cycle is only four. Accordingly, the transfer transistors of the overall memory cells are completely examined in 1024 cycles, which means that the transfer transistor of each memory cell receives a voltage stress for only 1/1024 of a time period for which each transistor in the peripheral circuit receives the voltage stress. This is undesirable in light of the aim of screening to detect and remove a defective device.
Further, in recent DRAMs, the capacitor electrode of each memory cell is generally supplied with a half V.sub.CC /2 of the power source voltage. Thus, a relatively low electric field is applied thereto, and therefore no reliability problems associated with a thin capacitor insulting film will occur. On the other hand, about 3/2 of the power source voltage V.sub.CC is applied to the gate of a transistor. In this case, even though a relatively high electric field is applied, a reliability problem may exist if the gate oxide film of the transistor is thick. Therefore, it is necessary to screen a transistor by applying a high voltage (such as the transfer transistor of a memory cell). However, in the case of the transfer transistor, screening is performed once in 1024 cycles as described above, which means that sufficient screening cannot be carried out.
In addition, if the degree of integration of a DRAM is, for example, quadrupled, the refresh cycle is doubled. That is, the higher the degree of integration, the longer the burn-in test. In summary, the conventional device is disadvantageous in that a voltage stress is applied to the transfer transistor of each memory cell only at low frequency.